1. Field of the Invention
The present invention relates to a method for testing a semiconductor integrated circuit used for evaluating the finished quality of the semiconductor integrated circuit and to a method for verifying design rules.
2. Description of the Related Art
As a conventional method for evaluating the finished quality of a semiconductor integrated circuit, measurement conducted by using PCMs (process control monitors) provided on a semiconductor wafer is applied as shown in FIG. 9.
DC characteristics (current values) of semiconductor wafers can be evaluated by using PCMs; that is, when values measured by using PCMs are below specified values, wafers are judged as being defective (see JP-A No. 2002-257903).
However, in the evaluation method using PCMs, it is impossible to check for defects in AC characteristics such as SI faults (crosstalk faults and IR-DROP faults) and delay faults which tend to increase in recent years as design rules become finer. Besides, PCMs are provided at only several spots on semiconductor wafers, which makes it impossible to evaluate the finished quality of all the semiconductor integrated circuits on semiconductor wafers.